Last month, Ultratech, a relatively unknown company to me, clinched the prestigious 2007 Advanced Packaging Award (APA) in the category of 3D Packaging. From the website of Ultratech, I get to know that this company is a photolithographic equipment maker founded in 1979. Compared to the more well-known photolithographic makers like ASML and Nikon, what makes this small company standing out? The answer is Ultratech’s AP300 Dual-Side Alignment (DSA) lithography system. The system uses a very innovative front-side infrared (IR) approach to perform dual-side alignment, achieving front-to-back overlay of less than 2 microns over a 300-mm wafer. As a result, it is possible to meet the stringent alignment requirement for through-silicon via (TSV) process on 300-mm wafers.

TSV technology is the key enabling process for fabricating 3D chips. In April this year, IBM announced that they were close to commercialize 3D chips based on TSV process which allows them to create high-bandwidth connections between two or more chips in a stacked packaging format (Ref). There are a number of key players working on TSV technology development, including Intel (Ref) and even our local Institute of Microelectronics (Ref). Since 2002, IME has worked with 24 industry partners on various projects related to TSV technology. In Q4 2007, IME will initiate a project to develop TSV technology for large die Cu/low-k chip with very fine pitch interconnection.

Below is a very interesting video interview of Arthur W. Zafiropoulo, Chairman, Chief Executive Officer and President of Ultratech by VLSI Research Inc. Zafiropoulo talked about how his company differentiates itself from the big competitors and thus able to capture the niche market of TSV technology.

IBM announced few days ago that they would change the microprocessor research strategy radically (Ref). Instead of using simple test chips to prove out their research concepts, IBM plans to use real chips with billion of transistors as test vehicles to drive its semiconductor research. Reasons quoted being the cost of wrong research decision, such as tool/process selection, can be extremely detrimental to subsequent development these days. By using a real chip, subtle failure modes and yield problems could be detected early. I guess IBM must have learned a lot of manufacturability tips from its Common Platform Alliance partners

I found the following video from VLSI Research Inc. This is a very interesting website with many good stuff. In this video, Steve Longoria, IBM vice president of Semiconductor Platforms, discusses the collaboration among IBM, Chartered, and Samsung in the open Common Platform technology initiative, and how the move is shaking up the industry’s traditional closed model. You can also read more about the history of Common Platform Alliance from this Ref.