Jun

7

DAC 2007 - The Ecogarden of Fabless, EDA and Foundries

Filed Under Chip Design, EDA and IP, Foundry, Movers and Shakers, Video Gallery, Yield Mgt and DFM | Leave a Comment

This year Design Automation Conference (DAC) 2007, the largest EDA event, is held from 4-8 June at the San Diego California, US. EETimes have conducted a series of video interviews with DAC 2007 key participants, including Rajeev Madhavan (Chairman and CEO of Magma), Aart de Geus (Chairman and CEO of Synopsys), Wally Rhines of Mentor Graphics, Isadore Katz (CEO and Chairman of CLK Design Automation), Ted Vucurevich of Cadence, Gary Smith of Gary Smith EDA, Xerxes Wania of Sidense, Jan Rabaey and others. The interviews cover a wide spectrum of topics ranging from the megatrends in EDA industry to DFM. One thing that catches my attention is how much TSMC has engaged EDA on their advanced technology programs (Ref1, Ref2, Ref3) . Evidently, foundries which offer strong EDA and DFM supports to fabless in order to achieve first silicon success will have a strong competitive advantage.

Watch the following insightful DAC 2007 videos interiviews from EETimes:

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Feb

11

High Demand for Low Power

Filed Under Chip Design, EDA and IP, Microprocessor, Semiconductor Industry | Leave a Comment

In the past, low power design is more of a concern for portable and mobile devices. However, low power design is now also critical for wired devices with constant power supply such as servers. It is contributing significantly to monthly electrical bills for cooling off these hot microchips, and also adding extra costs on packaging. The problems of low power design and power management are increasingly accentuated as designs migrate to sub-90nm processes. Many tiny leakages start to crop up and add up to a significant amount. Jonathan Koomey, consulting professor at Stanford University and one of the world’s foremost experts on electricity use in datacenters, said:

“Datacenter managers often tell me how important power management technology is for staying within their energy budgets…Having the ability to significantly reduce power at idle times is increasingly critical, particularly for datacenters that have extreme fluctuations in workloads from peak to off-peak times.”

Cadence Low Power Solution

On the other hand, the challenges for low power chip design brings great opportunities to the whole semiconductor industry, ranging from IDM, pure design houses, EDA, and packaging companies. In fact, one of key success factors of AMD is breaking into the server market through low power server microprocessors in the early ’00s. Just a few days back, AMD introduces another series of energy-efficient new Opteron processors running 2.6GHz and working within a 68 watt thermal envelope for densely packed data centers. Cadence also claims to offer the industry first complete solution for the design, verification, and implementation of low-power chips. Listen to the following Cadence podcast to gain more insight on Cadence Low Power Solution. [audio:http://media1.podtech.net/download.php?file=media/2007/01/PID_001910/Podtech_Cadence_NeilHandmixdown.mp3]

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