The world’s largest contract chipmaker has announced the readiness of its 40 nm manufacturing process technology for both a general purpose and low-power applications. TSMC plans to offer low-power 40nm technology for wireless and portable devices, and general-purpose 40nm technology for CPUs, GPUs, FPGA and other high-performance consumer devices. The company already has orders for such chips from customers. Production is expected to begin in the second quarter of 2008. (Ref).

TSMC claims that the its 40nm technology has the smallest footprint in the industry with 2.35× higher raw gate density and a SRAM cell size of 0.242 µm2. In addition, the 40nm technology offers significant saving in power as compared to its 45nm technology. The 40 nm process uses a combination of 193 nm immersion photolithography and ELK (Extreme Low-k) material. The 40G and LP processes will initially run in TSMCs Fab 12 and will be transferred to Fab 14 as demand ramps (Ref).

EDN Executive Editor Ron Wilson pointed out an interesting observation that the gap between TSMC 45nm and 40nm is surprisingly short, just 2Q difference (Ref). TSMC 45nm technology was ready in Sep 2007, and its 40nm technology is now ready in Mar 2008. Ron suggested that this probably was TSMC’s strategy to engage the fabless customers, such as Qualcomm and Altera, to 45nm as early as possible despite the 45nm might not be quite ready last year. The real production-ready process is actually the 40nm technology. The following video showed TSMC presentation to Altera on 45nm few months ago.

TI and STMicro have announced plans to stop internal technology development at 45nm and use foundry supplied processes at 32nm and below (read more on TI news and STMicro news). It does not necessarily mean that both IDMs will go fabless, but they claim that they would employ the foundry technology as a starting platform to develop valued-added derivatives in their own fabs. There are certainly compelling motivations behind this new strategic initiative:

• In term of leading edge logic technology, leading foundries like TSMC, UMC and Chartered have more or less catch up with the leading IDMs. Therefore, the differentiating advantages for IDMs to own their process and manufacturing technology is starting to erode very fast.
• The R&D cost of developing leading edge process technology is escalating exponentially for 45nm technology and below. A number of companies, both IDM and foundries, are now relying on alliance to reduce R&D cost and risk. However, with various partners (NXP and Freescale) exiting from the Crolles2 alliance, STMicro will find it difficult to finance the 32nm technology development.
• TI has successfully pursued a multiple foundry strategy for manufacturing outsourcing. The multiple foundry strategy is effective to hedge the outsourcing risk, reduce operational cost and increase bargaining power with foundries. To date, TI have qualified TSMC, UMC, SMIC, and now Chartered Semiconductor for manufacturing outsourcing.
• IDMs are facing increasing pressure to compete with Fabless Design Houses or Integrated Fabless Manufacturers (IFM), such as Broadcom, Xilinx, Altera and Qualcomm, which focus on SoC design and leave foundries to drive process technology development. To improve their ROI, IDMs are betting more on derivative/differentiating process development, like RF and analog, in their own Fabs.

TI has also announced that they would close down its 8″ k-fab in Dallas. Most likely its 12″ r-fab at Richardson will be the last leading-edge Fab built by TI. Will we see more IDMs follow TI and STMicro’s footsteps? Let’s see.