About a week ago, Chip Estimate Corporation, a EDA company offering IP search, announced the launch of Common Platform Intellectual Property (IP) Portal. This portal offers IC designers a complete catalog of 90-nanometer (nm), 65nm and 45nm IPs that have been developed for the Common Platform(Ref).

What exactly is this Common Platform? This is a relatively new ecosystem concept. Common Platform in essence is a multi-foundry sourcing ecosystem model conceived by IBM, Chartered and Samsung. It allegedly offers chip designers and vendors an unprecedented choice of “one-design, multi-source”. Traditionally, chip companies which opt for multi-foundry sourcing strategy have to expend considerable internal resource to re-design their chips using respective PDKs (Process Design Kits) and IP for different foundries. This is because different foundries provides different spice models, design rules and DFM rules, as well as foundry-specific IP. This is a hurdle for multi-foundry sourcing strategy despite the benefits of hedging supplier risk and leveraging on price. Common Platform aims to fulfill this need of chip designers.

At the heart of the Common Platform is the bulk CMOS foundry process technology that is jointly developed by IBM, Chartered, and Samsung. All the Common Platform foundries will offer identical spice models, physical design rules, design manuals, electrical specs for the process technologies which span from 90nm to 32nm. Common Platform is also supported by a comprehensive ecosystem of design enablement and implementation partners from the EDA, IP, and design services industries. There are a lot of common tools and IPs offered to customers. With Common Platform, chip designers and vendors could now save considerable resource with one single design and GDSII, and yet enjoy world-wide multi sourcing benefits.

The Common Platform was exhibited in the FSA’s Suppliers Expo & Conference held on the 12 Sep at the Santa Clara, California. Below is a video in which Marnie Mar from IBM talked about Common Platform in the FSA Conference. Click here for more information on the Common Platform - www.commonplatform.com. Excellent video introduction on Common Platform is also available here.

In the past, low power design is more of a concern for portable and mobile devices. However, low power design is now also critical for wired devices with constant power supply such as servers. It is contributing significantly to monthly electrical bills for cooling off these hot microchips, and also adding extra costs on packaging. The problems of low power design and power management are increasingly accentuated as designs migrate to sub-90nm processes. Many tiny leakages start to crop up and add up to a significant amount. Jonathan Koomey, consulting professor at Stanford University and one of the world’s foremost experts on electricity use in datacenters, said:

“Datacenter managers often tell me how important power management technology is for staying within their energy budgets…Having the ability to significantly reduce power at idle times is increasingly critical, particularly for datacenters that have extreme fluctuations in workloads from peak to off-peak times.”

On the other hand, the challenges for low power chip design brings great opportunities to the whole semiconductor industry, ranging from IDM, pure design houses, EDA, and packaging companies. In fact, one of key success factors of AMD is breaking into the server market through low power server microprocessors in the early ’00s. Just a few days back, AMD introduces another series of energy-efficient new Opteron processors running 2.6GHz and working within a 68 watt thermal envelope for densely packed data centers. Cadence also claims to offer the industry first complete solution for the design, verification, and implementation of low-power chips. Listen to the following Cadence podcast to gain more insight on Cadence Low Power Solution. [audio:http://media1.podtech.net/download.php?file=media/2007/01/PID_001910/Podtech_Cadence_NeilHandmixdown.mp3]