Amid the financial turmoil and economic slowdown, Applied Material, the world largest semiconductor equipment maker, had generously hosted a Applied Material Tech Forum (AMTF) at Raffles City Convention City, Stamford Hotel, Singapore on this Tuesday 4 Nov 2008. I attended the forum with some other colleagues. From the lunch break, I learned that Applied Material has cut all expenses except for the Tech Forum. Kudos to Applied Material!!

I was more impressed by the high standard speeches given by the invited speakers in the morning session, partly because the morning session speeches were kind of overview talk and easier to understand, while the afternoon session speeches were more technical and harder to grasp for the non experts.

One interesting point brought up by Dr. Simon Yang from Chartered Semiconductor was that there was a silver lining in this economic slowdown. He argued that aggressive CMOS scaling and the migration to 12″ wafer from 8″ wafer have significantly increased the capacity and supply, however the demand has not been able to keep up the increased capacity and supply. As a result, the foundry has suffered from the rat race of CMOS scaling and 12″ wafer migration. He further claimed that CMOS scaling will inevitably slow down due to the inherent physical limitations of gate oxide and lithography. The brake in CMOS scaling might help to re-balance the equation of supply and demand. In addition, Simon brought up an interesting point that scaling of the interconnect won’t help in reducing in RC and the low-k dielectric would most likely pegged at the sweetspot of 2.5. Another interesting point that rang a bell in me was that was that high-k/metal-gate was needed primarily because it helps to reduce Vt variability which is the main hurdle of CMOS scaling and in turn lower the SRAM Vmin.

I also picked up an interesting point by Dr. Reza Arghavani, Applied Material Fellow. He was hinting that the IBM’s gate first approach might face a big problem as compared to Intel’s gate last approach. The Intel’s gate last approach uses dual metal and single dielectric, in contrast the IBM’s gate first approach employs single metal and dual dielectric. However, IBM team is facing a big problem to find the right dielectric for PMOS.

Below is a commercial video from AMAT on their new venture to solar market.

The biggest semiconductor trade show in North America, SEMICON WEST 2008 has concluded couple of days ago (15-17 July). One of impending issues facing the semiconductor industry is the lithography solutions for 32nm and 22nm. It is pretty obvious now that EUV lithography will not be deployed for 32nm, and most likely will not be ready for 22nm as well. On the other hand, the immersion lithography technology which has served the semiconductor industry pretty well for 45-40nm will face its own limitations for 32nm and beyond. To bridge the gap for 32nm and 22nm before EUV lithography comes on board, the semiconductor industry is now betting on double patterning lithographic technology coupled with 193nm immersion lithography. However, as AMD Fellow Harry Levinson aptly summarized the current challenges of DP technology as “double patterning doubles the troubles” (Ref).

There are a number of variants for double patterning technology, such as double-exposure; trench double-patterning; line double-patterning; litho-etch-litho-etch, spacer and others. Whatever the variants, the biggest concerns with double-patterning technology are cost and overlay, particularly the overlay between the two exposures. To mitigate the overlay constraints, AMAT has introduced the Self-Aligned Double Patterning (SADP) Scheme. Samsung Electronics and Hynix Semiconductor Corp have announced they would use SADP for their 3x generation NAND flash. The IM Flash also reported that it would employ something similar to SADP for the 34nm memory devices (Ref).

During the SEMICON WEST 2008, IMEC announced a new variant of the double patterning technology which significantly reduces the cost. The new process first exposes the resist with the first pattern, apply a chemical enhancement to freeze that pattern into the material, expose the second pattern, and then develop and etch the resist normally. The big advantage of this approach is that the wafer stays on the litho track for both exposures. It doesn’t have to go off to a separate etch track and then back onto the litho track. (Ref)

On the other note, ASML has rolled out a new generation of 193-nm immersion scanner for double-patterning applications, Twinscan XT:1950i during the SEMICON WEST. It has an overlay below 4-nm and throughput of 175 wafers an hour. The system uses a lens with the same 1.35 numerical aperture (NA) as its predecessor, however the resolution has improved from 40 nm to 38 nm, which effectively provides a 10% gain in wafer area available for chips (Ref). You can watch a videos ads from ASML of this system below.