When Intel announced that they would use dry lithography only for 45nm technology node and delay the deployment of immersion lithography to 32nm technology node, I guess the rest of the chip makers in the world were probably taken aback and wondered how Intel manage to print a 45nm feature on a wafer without using high-NA immersion lithography. Some might guess Intel is probably using double patterning (DP) technique to get around the resolution limitation of dry lithography. I am pretty curious on this topic and did some googling to try to find out. It seems that this amazing feat comes from an innovative technology known as Computational Lithography, invented by Intel.

One of the key persons behind the invention of Computational Lithography is Yan Borodovsky, Intel Senior Fellow and Director of Advanced Lithography in Intel’s Technology and Manufacturing Group. He is responsible for directing Intel’s multi-generational advanced lithography definition and progress. According to Borodovsky, in the case of critical layers for 45nm logic, the use of dry lithography instead of immersion lithography at 193nm lowered costs by 27%.

The basic idea of Computational Lithography goes something like this (Ref). The desired chip pattern is inverted mathematically using Maxwell’s equations to define the photomask geometry that best projects that image. You could learn more about computational lithography from the following video interview of Yan Borodovsky by VLSI Research. As shown in the figure above, the mask is formed by arrays of sub resolution pits etched into the fused silica substrate in a grid pattern optimized by the inversion computation. The actual mask pattern may bear little resemblance to the design but nevertheless results in the desired photoresist pattern. The algorithm of such inversion computation is the secret sauce of Intel and to perform a full-chip computation would typically take million CPU hours.

I also think that there is a potential opportunity for foundry, maskshop and EDA, or even startups, to provide inversion computation service to design houses.

In my previous blog, I posted Semiconductor International podcasts on SPIE 2007 Advanced Lithography Conference. Interestingly, Solid State Technology also conducted a series of video interviews with leading industrial participants in the same conference. It seems to me that the industry is indeed struggling to find ways to extend 193nm immersion beyond 32nm half-pitch. Some bet on new material like high-index lens or fluid materials with suitable photoresists, while others are hedging their risks by looking at EUV litho. Watch the following videos interview to gain insights into where the industry is heading…

1. Franklin Kalk, CTO Toppan Photomasks
2. Harry Levinson, Manager of Strategic Lithography Technology and AMD Fellow AMD
3. Paul van Attekum, SVP & Business Unit Manager, Incubator Products ASML
4. Bob Akins, Co-founder, Chairman, CEO Cymer
5. Kurt Ronse, Director of Lithography IMEC
6. Bob Naber, Product Marketing Director of RET Solutions Cadence Design Systems
7. Lars Liebmann, Distinguished Engineer, Design for Manufacturability IBM
8. Hans Stork, SVP, CTO TI
9. John Sturtevant, RET Technology Support Manager Mentor Graphics
10. Michael Lercel, Lithography Director SEMATECH (IBM assignee)
11. Gary Smith, Chief Analyst Gary Smith EDA
12. Axel Nackaerts, Senior Engineer IMEC