Jun

30

Highlights of VLSI Symposium 2008

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I have captured some of the highlights of 2008 Symposium on VLSI Technology here:

  • Continuously driving incremental performance improvement in planar CMOS transistor performance is always one of the themes in VLSI Technology Symposium. This year, a number of companies have reported such efforts. For example, Toshiba reported that F and N co-implant at the halo implantation help could help to reduce the external resistance and improve NFET drive current. For pFET, Toshiba and IBM jointly announced a new Twisted Direct Silicon Bonding Technology to achieve higher hole mobility (Ref).
  • AMAT and TSMC reported a novel low-K spacer technology featuring CVD-SiBCN material with low dielectric constant of 5.2 and film stress of 430MPa to boost AC and DC CMOS performance.
  • The decade-old W contact technology is approaching its life limit. As the contact hole gets smaller, contact resistance is increasing, partly due to the contact barrier material. Various W replacements have been sought after. Among them Cu is the most desirable since wealth of knowledge on Cu technology has been built up over the last decade. This year, NEC reported a Direct Low-K/Cu Dual Damascene Contact Lines technology that can significantly improved the RO improved by approximately 7%.
  • Intel divulged more details on its Nehalem chip and 45nm high-k/metal-gate technology. Intel claimed that stress enhancement due to “gate last” increases the stress benefit of eSiGe.The amount of Ge in the eSiGe has also increased from 22% in 65nm tech to 30% in 45nm technology. In addition, Intel also employs trench contact in NMOS to compensate for the loss of tensile strain from the absence of Tensile stress layer. The trench contact also has an added benefit of lowering the contact resistance by >50%. Another notably piece of work by Intel is the Floating Body Cell (FBC) for cache memory. The FBC technology could potentially be introduced at the 16 nm node and further scaled to the 10 nm technology generation (Ref). All together, Intel contributed 5 papers to this year Symposium.

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Apr

16

IBM Alliance Touts 32nm High-k/Metal-Gate Ready

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IBM and its Fishkill alliance development partners, including Chartered Semiconductor, Freescale, Infineon, Samsung, STMicroelectronics and Toshiba announced two days ago that they have made a significant breakthrough in the high-k/metal-gate (HKMG) process that results in 35 percent performance improvements on their 32nm technology as compared to 45nm technology at the same operating voltage. The IBM alliance also claims that they are ready for early customer engagement to use the new 32nm HKMG process. (Ref).

In contrast to Intel HKMG process which employs a gate-last approach (also known as replacement gate process), IBM alliance is using a more conventional gate-first approach for HKMG process. While the gate-first approach is simpler, more scalable, and migrate-able (easier to port designs from previous generation) as compared to gate-last approach, IBM’s gate-first HKMG process development is apparently lagging far behind Intel’s gate-last HKMG process which has already been in mass production since 2H 2007. One underlying significance from the above IBM alliance joint statement is that the alliance is now ready to catch up with Intel and TSMC in 32nm process development. It also boosts the confidence of the alliance in future joint development. One of alliance member, Chartered Semiconductor has just extended the joint development collaboration with IBM to include 22-nanometer CMOS (Ref).

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