About a week ago, Chip Estimate Corporation, a EDA company offering IP search, announced the launch of Common Platform Intellectual Property (IP) Portal. This portal offers IC designers a complete catalog of 90-nanometer (nm), 65nm and 45nm IPs that have been developed for the Common Platform(Ref).

What exactly is this Common Platform? This is a relatively new ecosystem concept. Common Platform in essence is a multi-foundry sourcing ecosystem model conceived by IBM, Chartered and Samsung. It allegedly offers chip designers and vendors an unprecedented choice of “one-design, multi-source”. Traditionally, chip companies which opt for multi-foundry sourcing strategy have to expend considerable internal resource to re-design their chips using respective PDKs (Process Design Kits) and IP for different foundries. This is because different foundries provides different spice models, design rules and DFM rules, as well as foundry-specific IP. This is a hurdle for multi-foundry sourcing strategy despite the benefits of hedging supplier risk and leveraging on price. Common Platform aims to fulfill this need of chip designers.

At the heart of the Common Platform is the bulk CMOS foundry process technology that is jointly developed by IBM, Chartered, and Samsung. All the Common Platform foundries will offer identical spice models, physical design rules, design manuals, electrical specs for the process technologies which span from 90nm to 32nm. Common Platform is also supported by a comprehensive ecosystem of design enablement and implementation partners from the EDA, IP, and design services industries. There are a lot of common tools and IPs offered to customers. With Common Platform, chip designers and vendors could now save considerable resource with one single design and GDSII, and yet enjoy world-wide multi sourcing benefits.

The Common Platform was exhibited in the FSA’s Suppliers Expo & Conference held on the 12 Sep at the Santa Clara, California. Below is a video in which Marnie Mar from IBM talked about Common Platform in the FSA Conference. Click here for more information on the Common Platform - www.commonplatform.com. Excellent video introduction on Common Platform is also available here.

Right after DAC 2007 last week, we are hit by a big news in EDA industry. Mentor Graphics, the third-largest EDA company in the semiconductor industry, has made a bold move to acquire Sierra Design Automation with a price tag of $90 million (Ref). This acquisition will definitely strengthen Mentor’s market leadership in DFM, and may even propel Mentor to the top league. Everyone knows that there is a big gap in DFM to meet the complexities of process and design interaction for 65nm and 45nm technology nodes. But very few could come out with a viable DFM solution. One of them is Sierra Design Automation. It’s flagship product Olympus-SoC, an advanced manufacturing-driven place-and-route system, claims to embed variation-aware timing, optimization, and litho modeling together to address OPC and RET effects early in the design cycles. Walden C. Rhines, CEO and chairman of Mentor Graphics said in the press conference (Ref):

Our leading-edge customers are telling us that they need a design-to-fab flow capable of handling dozens of process corners and multiple modes, all while addressing manufacturability challenges to achieve manufacturing closure of their designs. Mentor’s and Sierra’s leadership in these areas make us a natural fit. The acquisition of Sierra expands Mentor’s leadership in DFM, and provides the integration that customers need between physical design, and back-end verification and yield-enhancement.

Watch the EETimes video commentary on this M&A.