About a week ago, Chip Estimate Corporation, a EDA company offering IP search, announced the launch of Common Platform Intellectual Property (IP) Portal. This portal offers IC designers a complete catalog of 90-nanometer (nm), 65nm and 45nm IPs that have been developed for the Common Platform(Ref).

What exactly is this Common Platform? This is a relatively new ecosystem concept. Common Platform in essence is a multi-foundry sourcing ecosystem model conceived by IBM, Chartered and Samsung. It allegedly offers chip designers and vendors an unprecedented choice of “one-design, multi-source”. Traditionally, chip companies which opt for multi-foundry sourcing strategy have to expend considerable internal resource to re-design their chips using respective PDKs (Process Design Kits) and IP for different foundries. This is because different foundries provides different spice models, design rules and DFM rules, as well as foundry-specific IP. This is a hurdle for multi-foundry sourcing strategy despite the benefits of hedging supplier risk and leveraging on price. Common Platform aims to fulfill this need of chip designers.

At the heart of the Common Platform is the bulk CMOS foundry process technology that is jointly developed by IBM, Chartered, and Samsung. All the Common Platform foundries will offer identical spice models, physical design rules, design manuals, electrical specs for the process technologies which span from 90nm to 32nm. Common Platform is also supported by a comprehensive ecosystem of design enablement and implementation partners from the EDA, IP, and design services industries. There are a lot of common tools and IPs offered to customers. With Common Platform, chip designers and vendors could now save considerable resource with one single design and GDSII, and yet enjoy world-wide multi sourcing benefits.

The Common Platform was exhibited in the FSA’s Suppliers Expo & Conference held on the 12 Sep at the Santa Clara, California. Below is a video in which Marnie Mar from IBM talked about Common Platform in the FSA Conference. Click here for more information on the Common Platform - www.commonplatform.com. Excellent video introduction on Common Platform is also available here.

When Intel announced that they would use dry lithography only for 45nm technology node and delay the deployment of immersion lithography to 32nm technology node, I guess the rest of the chip makers in the world were probably taken aback and wondered how Intel manage to print a 45nm feature on a wafer without using high-NA immersion lithography. Some might guess Intel is probably using double patterning (DP) technique to get around the resolution limitation of dry lithography. I am pretty curious on this topic and did some googling to try to find out. It seems that this amazing feat comes from an innovative technology known as Computational Lithography, invented by Intel.

One of the key persons behind the invention of Computational Lithography is Yan Borodovsky, Intel Senior Fellow and Director of Advanced Lithography in Intel’s Technology and Manufacturing Group. He is responsible for directing Intel’s multi-generational advanced lithography definition and progress. According to Borodovsky, in the case of critical layers for 45nm logic, the use of dry lithography instead of immersion lithography at 193nm lowered costs by 27%.

The basic idea of Computational Lithography goes something like this (Ref). The desired chip pattern is inverted mathematically using Maxwell’s equations to define the photomask geometry that best projects that image. You could learn more about computational lithography from the following video interview of Yan Borodovsky by VLSI Research. As shown in the figure above, the mask is formed by arrays of sub resolution pits etched into the fused silica substrate in a grid pattern optimized by the inversion computation. The actual mask pattern may bear little resemblance to the design but nevertheless results in the desired photoresist pattern. The algorithm of such inversion computation is the secret sauce of Intel and to perform a full-chip computation would typically take million CPU hours.

I also think that there is a potential opportunity for foundry, maskshop and EDA, or even startups, to provide inversion computation service to design houses.