About a week ago, Chip Estimate Corporation, a EDA company offering IP search, announced the launch of Common Platform Intellectual Property (IP) Portal. This portal offers IC designers a complete catalog of 90-nanometer (nm), 65nm and 45nm IPs that have been developed for the Common Platform(Ref).

What exactly is this Common Platform? This is a relatively new ecosystem concept. Common Platform in essence is a multi-foundry sourcing ecosystem model conceived by IBM, Chartered and Samsung. It allegedly offers chip designers and vendors an unprecedented choice of “one-design, multi-source”. Traditionally, chip companies which opt for multi-foundry sourcing strategy have to expend considerable internal resource to re-design their chips using respective PDKs (Process Design Kits) and IP for different foundries. This is because different foundries provides different spice models, design rules and DFM rules, as well as foundry-specific IP. This is a hurdle for multi-foundry sourcing strategy despite the benefits of hedging supplier risk and leveraging on price. Common Platform aims to fulfill this need of chip designers.

At the heart of the Common Platform is the bulk CMOS foundry process technology that is jointly developed by IBM, Chartered, and Samsung. All the Common Platform foundries will offer identical spice models, physical design rules, design manuals, electrical specs for the process technologies which span from 90nm to 32nm. Common Platform is also supported by a comprehensive ecosystem of design enablement and implementation partners from the EDA, IP, and design services industries. There are a lot of common tools and IPs offered to customers. With Common Platform, chip designers and vendors could now save considerable resource with one single design and GDSII, and yet enjoy world-wide multi sourcing benefits.

The Common Platform was exhibited in the FSA’s Suppliers Expo & Conference held on the 12 Sep at the Santa Clara, California. Below is a video in which Marnie Mar from IBM talked about Common Platform in the FSA Conference. Click here for more information on the Common Platform - www.commonplatform.com. Excellent video introduction on Common Platform is also available here.

Nanyang Technological University (NTU) has established the Institute for Sustainable Nanoelectronics (ISNE), an initiative aimed at developing next-generation embedded IC chips that consume over 100 times less energy, as well as cut design and production costs (Ref). What is this probabilistic CMOS or PCMOS? I have not heard about PCMOS before. So I did some googling on this subject.

The answer can be found in a paper entitled “”Ultra-Efficient (Embedded) SOC Architectures based on Probabilistic CMOS (PCMOS) Technology” presented at the Design, Automation and Test In Europe (DATE) 2006 Conference in Munich, Germany (Ref) by Prof Krishna Palem team. The PCMOS technology is invented by Prof. Krishna Palem. Prof. Krishna V. Palem currently holds Professorships in Electrical and Computer Engineering and in Computer Science, and he has been the founding director of the Center for Research in Embedded Systems and Technology (CREST) at the Georgia Institute of Technology, since 1999. He also holds the prestigious Fellow of the IEEE. Prof. Krishna V. Palem team claimed that their PCMOS approach would allow chips to use less energy and attain nano-dimensions, enabling longer battery life and faster turn-around in new designs. The idea behind PCMOS is captured by the following example:

Take for example streaming video application in a cell phone, it is unnecessary to conduct precise calculations. The small screen, combined with the human brain’s ability to process less-than-perfect pictures, results in a case where the picture looks good enough with calculations that are only approximately correct. This means that for slightly less-than-perfect picture quality, the user may need to charge the phone only every few weeks instead of every few days.

ISNE will receive a seed funding of $4million from NTU over two years (Strait Times article). NTU seems to be quite active in CMOS research recently. Last week, it signed up a deal with Chartered Semiconductor Manufacturing Ltd. to open a 100sq. m “Chartered@NTU” joint lab to focus on nanoscale CMOS process technology and reliability (Strait Time article). The new lab will also provide practical training and industrial exposure opportunities for NTU’s postgraduate students to work on real-world projects with engineers from Chartered. My guess is that the “resurrection” of CMOS research in NTU has to do with recent uptake in semiconductor FDI in Singapore (such as Qimonda and IM Flash) and also the recent commitment of EDB to invest S$8m to boost talents in wafer fabrication sector (Ref).

The following video will review power-optimized design methods and show how power is strongly tied to performance and that variability adversely effects power efficiency.